Substrate-engineered GGNMOS for low trigger voltage ESD in 65nm CMOS process

• DOI: 10.1016/j.microrel.2011.07.028
• Publication Date: 2011-08-04T02:05:42Z
• Authors: Fei Ma; Yan Han; Bo Song; Shurong Dong; Meng Miao; Jianfeng Zheng; Jian Wu; Kehan Zhu
• Keywords: 0103 physical sciences; 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; 01 natural sciences

Abstract A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.