Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
ddc:004
DATA processing & computer science
0103 physical sciences
01 natural sciences
info:eu-repo/classification/ddc/004
510
004
DOI:
10.1016/j.microrel.2013.12.012
Publication Date:
2014-02-12T10:15:14Z
AUTHORS (20)
ABSTRACT
Abstract The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.
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