3D to 2D perspectives - Traditional and new doping and metrology challenges at the nanoscale

• DOI: 10.1016/j.mssp.2023.107584
• Publication Date: 2023-05-15T13:28:33Z
• Authors: Margarita Georgieva; Nikolay Petkov; Ray Duffy

In this perspectives paper we will explore the doping state-of-the-art as it evolves for 3D to 2D structures and materials, following impact on metrology methods needed characterise them. Historically, silicon devices logic complementary metal-oxide-semiconductor (MOS) are built in bulk monocrystalline substrates. context substrates 3D, there is not electrostatic confinement associated with more technologically advanced device structures. The determination of technology figures-of-merit such sheet resistance, impurity concentration activation profiles versus depth, reverse bias leakage current track crystal quality post-doping process, have been typical evaluation. Since emergence FinFET, gate-all-around (GAA) logic, layered materials transition-metal-dichalcogenides (TMDs) MOS channel active areas, these awkward extract, or simply do apply usual sense. Logic devices, like transistors, depend processes lower access resistance thus drive performance, traditionally relied ion implantation introduce impurities substrate, which a physical bombardment that damages target material. Gentler rely in-diffusion an emerging category, most recently concept terminating functionalising (near-) surface semiconductor growing popularity, at least research labs. Likewise, require evolution adapt times, from conventional high-throughput techniques exploratory, albeit throughput, methods. Metrology relies upon high-sensitivity, large dynamic range detection, spatial resolution, well time- cost-efficient sample preparation post-analysis data interpretation. Driven primarily by continued development novel, scaled-down, truly unique architectures introduction novel nano-fabrication technology, portfolio dopant characterisation unremittingly enlarging its numbers. Herein, focus our discussion onto profiling fin nanowire FETs, relate analysis test vehicles arrays varying dimensions. Although reports detailing correlative use only few, present examples provided new information, absence overall description process inconclusive and, some cases, misleading.