An “artificial retina” processor for track reconstruction at the full LHC crossing rate

• DOI: 10.1016/j.nima.2015.10.048
• Publication Date: 2015-10-25T22:07:07Z
• Authors: A. Abba; F. Bedeschi; F. Caponio; R. Cenci; M. Citterio; A. Cusimano; J. Fu; A. Geraci; M. Grizzuti; N. Lusardi; P. Marino; M.J. Morello; N. Neri; D. Ninci; M. Petruzzo; A. Piucci; G. Punzi; L. Ristori; F. Spinella; S. Stracka; D. Tonelli; J. Walsh
• Keywords: Microsecond

Abstract We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.