The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

• DOI: 10.1016/j.nima.2022.167489
• Publication Date: 2022-10-01T23:06:32Z
• Authors: R. Ballabriga; J.A. Alozy; F.N. Bandi; G. Blaj; M. Campbell; P. Christodoulou; V. Coco; A. Dorda; S. Emiliani; K. Heijhoff; E. Heijne; T. Hofmann; J. Kaplon; A. Koukab; I. Kremastiotis; X. Llopart; M. Noy; A. Paterno; M. Piller; J.M. Sallesse; V. Sriskaran; L. Tlustos; M. van Beuzekom
• Keywords: Application-specific integrated circuit; Analog front-end

This manuscript describes the optimization of front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing noise and jitter. model presented here is validated with both circuit post layout simulations measurements on Timepix4 Application Specific Integrated Circuit (ASIC). analog procedure to optimize dimensions main transistors are described detail. most recent ASIC designed in framework Medipix4 Collaboration. It was manufactured 65 nm CMOS process, consists a four side buttable matrix 448 × 512 pixels 55 µm pitch. has gain ∼36 mV/ke- when configured High Gain Mode, ∼20 Low Mode. Equivalent Noise Charge (ENC) ∼68 e- rms ∼80 Mode respectively. In event driven mode incoming hits can be time stamped within ∼ 200 ps bin chip deal maximum flux 3.6 MHz mm−2 s−1. photon counting mode, up 5 GHz routine then used analyze performance limits terms jitter Sensitive Amplifiers