Bounding carry-in interference for synchronous parallel tasks under global fixed-priority scheduling

• DOI: 10.1016/j.sysarc.2018.08.004
• Publication Date: 2018-08-08T02:55:33Z
• Authors: Meiling Han; Tianyu Zhang; Qingxu Deng
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

Abstract With the increasing trend towards using multi-core architecture for embedded systems, the study of intra-task parallelism becomes attractive and desirable in the literature. Although several work studying parallel task models has been proposed, the problem of precise scheduling analysis for the multiprocessor case has largely remained open. To this end, this paper concentrates on analyzing the response time for synchronous parallel real-time tasks scheduled on a multiprocessor platform. Specifically, by exploring the feature of each interfering task, we first present an interference analysis method with higher accuracy compared to other existing work. Considering the cost brought by a high complexity of the proposed method, we further introduce techniques to increase the efficiency with an acceptable loss of accuracy which gives more flexibility to the system designers. Finally, we provide a dynamic programming algorithm for analyzing the schedulability of the whole task set based on our proposed interference analysis technique. Experimental evaluation validates the performance and efficiency of the proposed approach by comparing with other methods.