Formation of polycrystalline thin-film transistors with stacked poly-SiGe/poly-Si channel layer for low-voltage applications

• DOI: 10.1016/j.tsf.2011.01.085
• Publication Date: 2011-01-20T09:31:03Z
• Authors: M.H. Juang; C.W. Chang; Y.S. Peng; C.C. Hwang; J.L. Wang; D.C. Shye
• Keywords: Polycrystalline silicon; Leakage (economics)

Abstract A thin-film transistor (TFT) with polycrystalline SiGe/Si stacked channel layer has been proposed for low-voltage applications. For the stacked poly-SiGe/poly-Si channel layer, the resultant 1-μm TFT device can achieve an on/off current ratio above 7 orders and a relatively large on-state current at a low operating voltage, and also cause better transfer characteristics than both the conventional poly-Si and poly-SiGe channel layers. As compared to the poly-Si channel layer, the poly-SiGe channel layer may cause a larger on-state current at a small gate bias of 3 V, due to smaller difference between conduction band and intrinsic level. However, even at a small drain bias of 3 V, the poly-SiGe channel layer leads to an off-state leakage current of about 2 order larger than the poly-Si channel layer, since a smaller energy bandgap may cause more carrier field emission via trap states. As a result, when a poly-SiGe/poly-Si stacked channel layer is employed, the leakage current may be suppressed to a low level as that for the poly-Si channel layer, and the resultant on-state current at a low gate bias voltage can be close to a relatively high level as that for the poly-SiGe channel layer.