Improving the Performance of Aligned Carbon Nanotube-Based Transistors by Refreshing the Substrate Surface

Transconductance Subthreshold slope
DOI: 10.1021/acsami.2c22049 Publication Date: 2023-02-16T16:39:30Z
ABSTRACT
An aligned semiconducting carbon nanotube (A-CNT) array has been considered an excellent channel material to construct high-performance field-effect transistors (FETs) and integrated circuits (ICs). The purification assembly processes prepare a A-CNT require conjugated polymers, introducing stubborn residual polymers stress at the interface between A-CNTs substrate, which inevitably affects fabrication performance of FETs. In this work, we develop process refresh Si/SiO2 substrate surface underneath film by wet etching clean release stress. Top-gated FETs fabricated with show significant improvement especially in terms saturation on-current, peak transconductance, hysteresis, subthreshold swing. These improvements are attributed increase carrier mobility from 1025 1374 cm2/Vs 34% after refreshing process. Representative 200 nm gate-length exhibit on-current 1.42 mA/μm transconductance 1.06 mS/μm drain-to-source bias 1 V, swing (SS) 105 mV/dec, negligible hysteresis drain-induced barrier lowering (DIBL) 5 mV/V.
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