Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures

• DOI: 10.1038/s41467-024-45482-x
• Publication Date: 2024-02-07T07:05:24Z
• Authors: Qiyu Yang; Zheng-Dong Luo; Huali Duan; Xuetao Gan; Dawei Zhang; Yuewen Li; Dongxin Tan; Jan Seidel; Wenchao Chen; Yan Liu; Yue Hao; Genquan Han
• Keywords: Thermionic emission; Subthreshold slope

Abstract Two-dimensional (2D) semiconductor-based vertical-transport field-effect transistors (VTFETs) – in which the current flows perpendicularly to substrate surface direction are drive surmount stringent downscaling constraints faced by conventional planar FETs. However, low-power device operation with a sub-60 mV/dec subthreshold swing (SS) at room temperature along an ultra-scaled channel length remains challenging for 2D VTFETs. Here, we report steep-slope VTFETs that combine gate-controllable van der Waals heterojunction and metal-filamentary threshold switch (TS), featuring vertical transport thinner than 5 nm sub-thermionic turn-on characteristics. The integrated TS-VTFETs were realised efficient switching behaviours, exhibiting modulation ratio exceeding 1 × 10 8 average SS over 6 decades of drain current. proposed excellent area- energy-efficiency could help tackle performance degradation-device dilemma logic transistor technologies.