Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

• DOI: 10.1038/s41598-020-68547-5
• Publication Date: 2020-07-16T10:02:53Z
• Authors: Jiyong Woo; Tien Van Nguyen; Jeong Hun Kim; Jong-Pil Im; Solyee Im; Yeriaron Kim; Kyeong-Sik Min; Seung Eon Moon
• Keywords: Neuromorphic engineering; Margin (machine learning); Memristor

Abstract A crossbar array architecture employing resistive switching memory (RRAM) as a synaptic element accelerates vector–matrix multiplication in parallel fashion, enabling energy-efficient pattern recognition. To implement the function of synapse RRAM, multilevel resistance states are required. More importantly, large on/off ratio RRAM should be preferentially obtained to ensure reasonable margin between each state taking into account inevitable variability caused by inherent mechanism. The is basically adjusted two ways modulating measurement conditions such compliance current or voltage pulses modulation. latter technique not only more suitable for practical systems, but also can achieve multiple low range. However, at expense applying high negative aimed enlarging ratio, breakdown occurs unexpectedly. This stuck-at-short fault adversely affects recognition process based on reading and judging column changed input array, degrading accuracy. address this challenge, we introduce boost-factor adjustment fault-tolerant scheme simple circuitry that eliminates additional identify specific locations failed RRAMs array. Spectre circuit simulation performed verify effect Modified National Institute Standards Technology dataset using convolutional neural networks non-ideal arrays, where experimentally observed imperfective configured. Our results show accuracy maintained similar ideal case because interruption failure suppressed scheme.