Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

High-κ dielectric Equivalent oxide thickness
DOI: 10.1038/srep20907 Publication Date: 2016-02-10T10:24:00Z
ABSTRACT
Abstract The downscaling of the capacitance equivalent oxide thickness (CET) a gate dielectric film with high constant, such as atomic layer deposited (ALD) HfO 2 , is fundamental challenge in achieving high-performance graphene-based transistors low leakage current. Here, we assess application various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain uniform and pinhole-free ALD substantially small CET at wafer scale. effects modifications, N-methyl-2-pyrrolidone treatment introduction sputtered ZnO e-beam-evaporated Hf seed layers graphene, subsequent formation under identical process parameters were systematically evaluated. nucleation provided (which transforms during ALD) resulted conformal without damaging which suitable for CET. After verifying feasibility scaling down achieve ~1.5 nm from an array top-gated metal-oxide-graphene field-effect transistors, fabricated heterojunction tunnelling record-low subthreshold swing value <60 mV/dec 8″ glass wafer.
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