VLSI Design for High‐Precision Three‐Dimensional Depth Perception Chip

• DOI: 10.1049/cje.2021.04.009
• Publication Date: 2021-05-31T16:33:17Z
• Authors: GE Chenyang; YAO Huimin; ZHOU Yanhui; DENG Pengchao
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

This paper presents a Very large scale integration (VLSI) design method for Three-dimensional (3D) depth perception chip based on infrared coding structure light. The primary sub-modules on the chip contain the speckle pattern preprocessing module, block-matching disparity estimation, depth mapping and post-processing. The chip employs pipelining technology, and after Application specific integrated circuit (ASIC) verification, it proves that our chip has more advantages in performance of depth precision (12bits, 1mm @ 1m), image resolution (1280×960), time delay (less than 17ms), range limit (0.4~6m). It also can generate more stable and smooth depth map in real-time, which can be used in 3D recognition, motion capture or scene perception.