Design of a High-Speed Asynchronous Turbo Decoder

• DOI: 10.1109/async.2007.16
• Publication Date: 2007-04-02T20:44:51Z
• Authors: Pankaj Golani; Georgios D. Dimou; Mallika Prakash; Peter A. Beerel
• Keywords: Turbo code; Forward error correction; Turbo equalizer; Turbo; Robustness

This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction used applications where maximal information transfer is needed over limited-bandwidth communication link presence data corrupting noise. Specifically we designed an high-speed decoder that can be potentially new wireless communications protocols with close to OC-12 throughputs. The design has been implemented using static single-track-full-buffer (SSTFB) library IBM 0.18 mum technology provides low latency, fast cycle-time, and more robustness noise than previously studied single-track full-buffer (STFB). A synchronous counterpart same architecture comparison. results demonstrate variety network constraints, throughput per area. Moreover, support very low-latency constraints not achievable alternative.