Analysis and Implementation of Staggered Wire Bonding for LVDS Data and Large Power Transmission in CMOS Image Sensors

• DOI: 10.1109/iccs59502.2023.10367380
• Publication Date: 2023-12-29T19:28:28Z
• Authors: Bowen Ding; Zhiqiang Niu; Zhikun Chen; Weizhe Zhang; Bailin Zhang; Changhui Yang; Nanjian Wu; Liyuan Liu; Peng Feng
• Keywords: Line (geometry)

This paper presents a novel structure of staggered pad configuration for wire bonding to simultaneously transmit Low-Voltage Differential Signaling (LVDS) data and large power ultra-high speed global shutter(GS) CMOS image sensor(CIS). In this structure, the inner pads are high-density placed close pixel array achieve transmission small IR drop. The outer low-density in area chip with independent ring LVDS remove interference between CIS line circuit. Noise impact on signal has been modeled, analyzed simulated. A prototype GS proposed fabricated 110nm process. measurement results show that can provide 9.7 W at 250Mbps per channel.