A 12-bit 625 MS/s Time-interleaved Pipelined ADC

• DOI: 10.1109/icicm59499.2023.10365874
• Publication Date: 2023-12-25T19:40:58Z
• Authors: Yahan Yu; Peng Miao; Fei Li; Di Wang; Haotian Zhang; Ankang Ding
• Keywords: Spurious-free dynamic range; Linearity; Nyquist rate; Successive approximation ADC

This article presents a 12-bit 625 MS/s time-interleaved ADC analog-to-digital converter (ADC) that achieves an SFDR/SNDR of 64.47/59.08 dB near Nyquist rate. An input buffer with replica capacitor is employed to effectively drive the sampling high linearity. A bootstrapped switch operating at adopted eliminate timing mismatch and achieve Also, pipelined utilized as sub-ADC owing its balance rate revolution. The implemented in 45 nm CMOS technology 376 mW power consumption total layout area 850μm $\times$ 590μm.