Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

• DOI: 10.1109/tvlsi.2022.3146064
• Publication Date: 2022-02-15T02:08:07Z
• Authors: Rongmei Chen; Lin Chen; Jie Liang; Yuanqing Cheng; Souhir Elloumi; Jaehyun Lee; Kangwei Xu; Vihar P. Georgiev; Kai Ni; Peter Debacker; Asen Asenov; Aida Todri-Sanial
• Keywords: 0103 physical sciences; 01 natural sciences; 7. Clean energy

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a (CNT) SRAM array composed schematically optimized CNFET CNT interconnects. We consider interconnects inside metallic single-wall (M-SWCNT) bundles to represent metal layers 0 1 (M0 M1). investigate layout structure considering devices, M-SWCNT interconnects, electrode Palladium with (Pd-CNT) contacts. Two versions designs are explored compared terms performance, stability, power efficiency. Furthermore, implement 16 Kbit proposed cells, multiwall (MWCNTs) inter-cell Pd-CNT Such an shows significant advantages, read write overall energy-delay product (EDP), consumption, core area <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.28\times $ </tex-math></inline-formula> , notation="LaTeX">$0.52\times notation="LaTeX">$0.76\times respectively 7-nm FinFET-SRAM copper whereas noise margins 6% 12% larger than FinFET counterpart.