Scalable and Parallel Optimization of the Number Theoretic Transform Based on FPGA

• DOI: 10.1109/tvlsi.2023.3312423
• Publication Date: 2023-09-28T17:57:26Z
• Authors: Bin Li; Yunfei Yan; Yuanxin Wei; Heru Han
• Keywords: Modular exponentiation

In lattice-based postquantum cryptography (PQC), polynomial multiplication is complex and time-consuming, which affects the overall computational efficiency. addition, parameters of different algorithms require number theoretic transform (NTT) structures, limits versatility hardware design. To this end, article proposes scalable parallel optimization NTT based on a field-programmable gate array (FPGA). By analyzing algorithm flow NTT, inverse (INTT), pointwise (PWM), an FPGA loosely coupled structure designed, can be used to place butterfly units multiple pipelines in supports various modulo operations polynomial. improve computing efficiency scalability, key modules such as multipliers modular reduction are deeply optimized. Moreover, storage RAM channels carried out, alternate access control data multiplexing resources reduce resource consumption For SHA-3 algorithm, Keccak implemented serial–parallel hybrid manner hash modes. Finally, taking Dilithium example, through parallelization calculation cycle generation, signature, verification shortened. The experimental results analysis show that scheme shortens period while ensuring high frequency, time significantly better than other schemes. Furthermore, it support optimized moduli give full play advantages FPGA.