Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

• DOI: 10.1126/science.aaw5581
• Publication Date: 2019-04-25T23:06:15Z
• Authors: Elliot J. Fuller; Scott T. Keene; Armantas Melianas; Zhongrui Wang; Sapan Agarwal; Yiyang Li; Yaakov Tuchman; Conrad D. James; Matthew J. Marinella; J. Joshua Yang; Alberto Salleo; A. Alec Talin
• Keywords: 02 engineering and technology; 0210 nano-technology

Ionic floating-gate memories

Digital implementations of artificial neural networks perform many tasks, such as image recognition and language processing, but are too energy intensive for many applications. Analog circuits that use large crossbar arrays of synaptic memory elements represent a low-power alternative, but most devices cannot update the synaptic weights uniformly or scale to large array sizes. Fuller et al. developed an integrated device, ionic floating-gate memory, that has the gate terminal of a redox transistor electrically connected to a diffusive memristor. This low-power device enabled linear and symmetric weight updates in parallel over an entire crossbar array at megahertz rates over 10 9 write-read cycles.

Science , this issue p. 570