Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs

• DOI: 10.1142/s021812661850161x
• Publication Date: 2018-01-12T03:07:01Z
• Authors: Hao Wang; Lungui Zhong; Guocheng Zhang
• Keywords: Successive approximation ADC; Bit (key)

A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there no average switching power consumption. From fourth cycle, one-side double-level scheme or monotonic one utilized based on two bits. When bits are same, chosen. Otherwise, adopted. Thus, proposed method only requires 5.27 CV[Formula: see text] energy, 75.29% less compared to Sanyal and Sun one.