A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits

• DOI: 10.1145/1118299.1118322
• Publication Date: 2006-05-08T21:40:43Z
• Authors: Lili Zhou; Cherry Wakayama; Nuttorn Jangkrajarng; Bo Hu; C.-J. Richard Shi
• Keywords: Application-specific integrated circuit; Design flow; Standard cell; Low-power electronics; Transistor count

A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18μm depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D with about 8M transistors was simulated to have high throughput of 2Gb/s low power consumption only 430mW 6.4μm by 6.3μm die area. implementation is estimated offer more than 10x power-delay-area product improvement over its corresponding 2D implementation. This first large-scale ASIC fine-grain (5μm) vertical interconnects made possible jointly developing complete automated design flow from commercial 2-D combined the needed 3D-design point tools.