Reducing idle mode power in software defined radio terminals

• DOI: 10.1145/1165573.1165597
• Publication Date: 2006-10-18T22:04:00Z
• Authors: Hyunseok Lee; Trevor Mudge; Chaitali Chakrabarti
• Keywords: Idle

In this paper, we propose a processor which is optimized for idle mode operation of software defined radio (SDR) terminal. Since SDR terminal spends most its time in the mode, reducing power consumption directly translates to longer standby time. Workload analysis operations contemporary standards showed that these are dominated by FIR filtering, can be easily parallelized. This was used design processor. The key architectural components an SIMD unit parallel computations dominate workload, conventional scalar sequential computations, and control supports efficient data memory access loop control. modeled with Verilog synthesized using standard cells 0.13 micron technology. It consumes about 9mW at 1.08V.