Energy-efficient cache design using variable-strength error-correcting codes

• DOI: 10.1145/2000064.2000118
• Publication Date: 2011-06-28T17:34:50Z
• Authors: Alaa R. Alameldeen; Ilya Wagner; Zeshan Chishti; Wei Wu; Chris Wilkerson; Shih-Lien Lu
• Keywords: 0103 physical sciences; 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; 01 natural sciences; 7. Clean energy

Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail. Cell failures in large memory arrays (e.g., caches) typically determine Vccmin for whole processor. We observe that cache lines exhibit zero or at low voltages. few lines, especially caches, multi-bit and increase Vccmin. Previous solutions either significantly reduce capacity enable uniform error correction across all latency bandwidth overheads when amortizing cost error-correcting codes (ECC) over lines.