Memory access scheduling

• DOI: 10.1145/342001.339668
• Publication Date: 2004-07-22T06:26:10Z
• Authors: Scott Rixner; William J. Dally; Ujval J. Kapasi; Peter Mattson; John D. Owens
• Keywords: Memory bandwidth; Dram

The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with “3-D” structure banks, rows, columns characteristic contemporary DRAM chips. There is nearly an order magnitude difference between successive references to different within row rows bank. This paper introduces access scheduling, technique that improves performance by reordering exploit locality 3-D structure. Conservative reordering, first ready reference sequence performed, 40% for traces from five media benchmarks. Aggressive operations scheduled optimize bandwidth, 93% same set applications. Memory scheduling particularly important processors where it enables processor make most efficient use scarce bandwidth.