PIugSMART

• DOI: 10.1145/3479876.3481601
• Publication Date: 2021-10-05T15:14:45Z
• Authors: Alireza Monemi; Iván Pérez; Neiel Leyva; Enrique Vallejo; Ramón Beivide; Miquel Moretó
• Keywords: Encaminadors (Xarxes d'ordinadors); Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors; 0103 physical sciences; Low latency; Networks on a chip; Multihop bypass; Routers (Computer networks); Network-on-Chip; :Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]; SMART NoC; 01 natural sciences

The integration of many processing elements per die makes it more difficult to provide low latency in the Network-on-Chip (NoC). Multihop bypass proposals, such as SMART, attack this problem by allowing flits skip multiple routers path a single cycle, drastically reducing while preserving regular tiled layout. However, multihop are complex and relatively different from traditional NoC routers, since they rely on global broadcast signals allocation mechanisms. Additionally, maximum number nodes that can be bypassed within cycle is limited Critical Path Delay (CPD) NoC. Hence, practical mechanism must also minimize delay.