Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

• DOI: 10.1145/3575861
• Publication Date: 2022-12-09T12:10:15Z
• Authors: Francesco Minervini; Oscar Palomar; Osman Unsal; Enrico Reggiani; Josue Quiroga; Joan Marimon; Carlos Rojas; Roger Figueras; Abraham Ruiz; Alberto Gonzalez; Jonnatan Mendoza; Ivan Vargas; César Hernandez; Joan Cabre; Lina Khoirunisya; Mustapha Bouhali; Julian Pavon; Francesc Moll; Mauro Olivieri; Mario Kovac; Mate Kovac; Leon Dragic; Mateo Valero; Adrian Cristal
• Keywords: Register file; Vector processor

The maturity level of RISC-V and the availability domain-specific instruction set extensions, like vector processing, make a good candidate for supporting integration specialized hardware in processor cores High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, processing acceleration engine that represents core execution HPC challenge comes within EuroHPC initiative. It implements extension (RVV) 0.7.1 can be easily connected to scalar using Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements single register. is composed identical pipelines (lanes), each containing slice Register File functional units (one integer, one floating point). scheme hybrid in-order/out-of-order supported by register renaming arithmetic/memory decoupling. On stand-alone synthesis, reaches maximum frequency 1.4 GHz typical conditions (TT/0.80V/25°C) GlobalFoundries 22FDX FD-SOI. silicon implementation has total area 1.3 mm 2 estimated power ∼920 mW instance equipped with eight lanes.