MuTaTe

• DOI: 10.1145/764808.764830
• Publication Date: 2004-04-19T13:18:43Z
• Authors: Rolf Drechsler; Junhao Shi; Görschwin Fey
• Keywords: Netlist; Binary decision diagram

We present a technique to derive fully testable circuits under the Stuck-At Fault Model (SAFM) and Path-Delay (PDFM). Starting from function description as Binary Decision Diagram (BDD) netlist is generated by linear time mapping algorithm. Only one additional input inverter are needed achieve 100% SAFM PDFM. Experiments given show advantages of in comparison previously presented methods.