MuTaTe

• DOI: 10.1145/764825.764830
• Publication Date: 2004-02-04T15:48:02Z
• Authors: Rolf Drechsler; Junhao Shi; Görschwin Fey
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

We present a technique to derive fully testable circuits under the Stuck-At Fault Model (SAFM) and the Path-Delay Fault Model (PDFM). Starting from a function description as a Binary Decision Diagram (BDD) the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the the technique in comparison to previously presented methods.