A design flow for partially reconfigurable hardware

• DOI: 10.1145/993396.993399
• Publication Date: 2005-08-02T08:38:10Z
• Authors: Ian Robertson; James Irvine
• Keywords: Electrical engineering. Electronics Nuclear engineering; Electronic computers. Computer science; 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.