Asymmetrical Nine-Level Inverter Topology with Reduce Power Semicondutor Devices

• DOI: 10.12928/telkomnika.v16i1.8520
• Publication Date: 2018-04-05T14:05:05Z
• Authors: M. S. Arif; S.M. Ayob; Z. Salam
• Keywords: polarity changer; topology; multilevel inverter; 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; TK Electrical engineering. Electronics Nuclear engineering; reduced components

In this paper a new single-phase multilevel inverter topology is presented. Proposed capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging available switches and dc sources in fashion such that the maximum combination addition subtraction input obtained. To verify viability proposed topology, circuit model developed simulated Matlab-Simulink software. Experimental testing results laboratory, are A low frequency switching strategy employed work. The show to produce voltage, handling inductive load yields acceptable harmonic distortion content