A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si

• DOI: 10.1364/ofc.2018.m2d.2
• Publication Date: 2018-03-05T11:09:53Z
• Authors: Toshiki Kishi; Munehiko Nagatani; Shigeru Kanazawa; Shinsuke Nakano; Hiroaki Katsurai; Takuro Fujii; Hidetaka Nishi; Takaaki Kakitsuka; Koichi Hasebe; Kota Shikama; Yuko Kawajiri; Atsushi Aratake; Hideyuki Nosaka; Hiroshi Fukuda; Shinji Matsuo
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; 7. Clean energy

A low-power compact 4-channel transmitter consisting of a 65-nm CMOS cascode shunt LD driver and flip-chip-bonded 1.3-μm LD-array-on-Si achieves 25-Gbps 2-km-long SSMF error-free operation for each channel, with power consumption 1.37 mW/Gbps.