VLSI Architecture for Edge Detection of Leaf Images

• DOI: 10.14738/tecs.1302.18612
• Publication Date: 2025-04-23T08:25:29Z
• Authors: Gundla Sukanya; T. Satya Savithri

This paper proposed a new VLSI Architecture for Sobel Edge detector Cotton and Grape leaf images. is tested images using Verilog HDL Simulated Synthesized Xilinx Vivado tool results shown the low power area, utilized less than 0.01% of LUTs 0.13 w only. The same architecture also extended Prewitt Laplace detectors that utility area less.