Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling

• DOI: 10.1587/transele.e95.c.546
• Publication Date: 2012-04-02T04:19:57Z
• Authors: Benjamin DEVLIN; Makoto IKEDA; Kunihiro ASADA
• Keywords: Power gating; Gate array

A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of signaling allows the FPGA to operate at voltages down 370mV without any parameter tuning. We show both 2.6x total reduction and 6.4x performance improvement same time compared non-power gated SSFPGA, latest research 1.8x in power-delay product (PDP) 2x improvement. When a similar process we are able up 84.6x PDP also maximum throughput on SSFPGA achieved 0.6V, 27fJ/operation 264MHz.