A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

• DOI: 10.20944/preprints201806.0393.v1
• Publication Date: 2018-06-27T22:50:25Z
• Authors: Linlin Fang; Bingyi Li; Yizhuang Xie; He Chen
• Keywords: CORDIC

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode achieve variety of operations and replaces multiple single-mode CORDIC processors. A pipeline-parallel mixed architecture is proposed adapt different operations, which maximizes the sharing common hardware circuit achieves area-delay-efficiency. Compared with previous processors, consumption resources greatly reduced. As proof concept, we apply it 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error each phase function between software computation corresponding SAR result meet accuracy index requirements.