Low -Warpage Encapsulants for Wafer Level Packaging

• DOI: 10.23919/iwlpc52010.2020.9375882
• Publication Date: 2021-03-18T16:03:58Z
• Authors: Jay Chao; Rong Zhang; David Grimes; Kail Shim; Tu Do; Yijia Ma; Ramachandran K. T...
• Keywords: Wafer-level packaging; Package on package

Wafer level encapsulation has become increasingly important to build up components for mobile and high-performance computing applications. Ranging from system-in-package antenna modules high band-width memory device, many of those wafer-level applications demand new features encapsulant materials. Besides provide mechanical protection, encapsulants are preferred bring in extra features: a) reducing package warpage during processing; b) being EU REACH compliant, c) showing excellent flowability trench-fill or gap-fill. In our material development, these can be achieved a type filled epoxy system. The class maintains glass transition temperature (Tg), at the same typical semiconductor encapsulants, while demonstrating low-warpage process, an estimation more than 50% improvement encapsulants. Owing use fine fillers resin chemistry, gap-filling is possible. Combination good allows us serve better Some case studies will discussed, including: 1) using liquid compression molding (LCM) process encapsulate wafers that have built-in trench-gaps, fine-gaps, solder-bumps. 2) stencil printing trenched wafers. both routes, low-warpage, void-free gap-fill packages. Moreover, encapsulated test-vehicles passed JEDEC MSL-1 reliability conditions. results demonstrated this potential meet growing demands various