A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology

• DOI: 10.23919/vlsic.2017.8008466
• Publication Date: 2017-08-29T18:53:56Z
• Authors: Takahiko Ishizu; Shuhei Nagatsuka; Momoyo Yamaguchi; Atsuo Isobe; Yoshinori Ando; Daisuke Matsubayashi; Kiyoshi Kato; Hai Biao Yao; Chi Chang Shuai; Hung Chan Lin; J Y Wu; Masahiro Fujita; Shunpei Yamazaki
• Keywords: Megabit; Standby power; Memory cell

An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than zA (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-21</sup> A) was fabricated. In the gain cell, OSFET for write operation stacked over a SiFET read operation. The fabricated combination 60-nm and 65-nm CMOS processes. It achieves 140 MHz data retention more h. Its static power in standby state active are 31 μW 64 μW/MHz, respectively. long-term can reduce by gating. OSFET-based is applicable to devices requiring high performance as well power.