High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

• DOI: 10.23919/vlsit.2017.7998171
• Publication Date: 2017-08-09T20:18:06Z
• Authors: Yong Kyu Lee; Changmin Jeon; Hongkook Min; Boyoung Seo; Kwangtae Kim; Donghyun Kim; Kyungsoo Min; JongSung Woo; Hyunug Kang; YongSeok Chung; Minsu Kim; Jaejune Jang; KyongSik Yeom; Ji-Sung Kim; MyeongHee Oh; Hyosang Lee; Sunghee Cho; Duckhyung Lee
• Keywords: Flash ADC

We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture scaling word-line (WL) transistor. New type high-voltage transistor with LDD-first scheme is applied to enable further decoder block in Flash IP. Digital-Vdd (1.0V) read used by lowering threshold voltage (V <sub xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> HV without sacrificing break-down during P/E operation. By using module process concept, existing RF IP reused modification.