Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -

• DOI: 10.23919/vlsitechnologyandcir57934.2023.10185290
• Publication Date: 2023-07-24T17:36:33Z
• Authors: J.W. Han; S.H. Park; M.Y. Jeong; K.S. Lee; K.N. Kim; H.J. Kim; J.C. Shin; S.M. Park; S.H. Shin; S.W. Park; K.S. Lee; J.H. Lee; S.H. Kim; B.C Kim; M.H. Jung; I.Y. Yoon; H. Kim; S.U. Jang; K.J. Park; Y.K. Kim; I.G. Kim; J.H Oh; S.Y. Han; B.S. Kim; B.J. Kuh; J.M. Park
• Keywords: Dram; Universal Memory; Dynamic random-access memory; Data retention

For the past decades, density of DRAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond 10 nm process node increasingly poses reliability challenges. As Flash technology made a pivotal successful innovation via 3D NAND, may also adopt vertical stacking memory cells. Vertically stacked (VS-DRAM) continues to increase bit on die increasing number layers along with reducing transistor. In this paper, opportunities challenges VS-DRAM are discussed.