Smart Communication Using 2D and 3D Mesh Network-on-Chip

• DOI: 10.32604/iasc.2022.024770
• Publication Date: 2022-05-25T06:28:42Z
• Authors: Arpit Jain; Adesh Kumar; Anand Prakash Shukla; Hammam Alshazly; Hela Elmannai; Abeer D. Algarni; Roushan Kumar; Jitendra Yadav
• Keywords: ModelSim; Virtex; MPSoC

Network on chip (NoC) is an integrated communication system (SoC), efficiently connecting various intellectual property (IP) modules a single die. NoC has been suggested as enormously scalable solution to overcome the problems in SoC. The performance of depends several aspects terms area, latency, throughput, and power. In this paper, 2D 3D mesh Virtex-5 field-programmable gate array (FPGA) studied. design carried Xilinx ISE 14.7 behavior model followed based XY XYZ routing for respectively. functional simulation performed Modelsim 10.0 software. on-chip communicationis verified with different cluster sizes that pre-estimates hardware resources utilization FPGA. algorithm provides substantial platform designers issues configuration synthesis FPGA case multiple processing elements, routers, cache controllers are helpful embedded smart wireless communication.