Approximate Array Multipliers

• DOI: 10.3390/electronics10050630
• Publication Date: 2021-03-09T17:08:01Z
• Authors: Padmanabhan Balas...; Raunaq Nayar; Douglas L. Maskell
• Keywords: :Electrical and electronic engineering::Integrated circuits [Engineering]; low power; Arithmetic Circuits; multiplier; 02 engineering and technology; approximate computing; :Computer science and engineering::Hardware [Engineering]; arithmetic circuits; complementary metal-oxide-semiconductor (CMOS); 0202 electrical engineering, electronic engineering, information engineering; logic design; Approximate Computing; high speed

This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate multiplier followed different input and output assignments within multiplier. We consider a digital image denoising application show how combinations affect quality denoised images. several for synthesis. The were described Verilog hardware description language synthesized Synopsys Design Compiler using 32/28-nm complementary metal-oxide-semiconductor technology. results that compared to multiplier, one proposed viz. PAAM01-V7 achieves 28% reduction critical path delay, 75.8% power, 64.6% area while enabling production is comparable standard metrics such as total power dissipation, are given, error parameters provided, original image, noisy images also depicted comparison.