The Effect of Diluted N2O Annealing Time on Gate Dielectric Reliability of SiC Metal-Oxide Semiconductor Capacitors and Characterization of Performance on SiC Metal-Oxide Semiconductor Field Effect Transistor

• DOI: 10.3390/electronics13030596
• Publication Date: 2024-01-31T15:44:24Z
• Authors: Zhihua Dong; Leifeng Jiang; Manqi Su; Chunhong Zeng; Hui Liu; Botong Li; Yuhua Sun; Qi Cui; Zhongming Zeng; Baoshun Zhang
• Keywords: Dielectric strength

We performed dry oxidation on n-type silicon carbide (SiC), followed by annealing in diluted N2O, and subsequently fabricated MOS structures. The study aimed to investigate the impact of different times trap charges near SiC/SiO2 interface reliability gate dielectric. Capacitance-voltage (C-V) current-voltage (I-V) measurements revealed that increasing time with N2O effectively reduces density electron traps interface, mitigates drift flat-band voltage enhances oxide breakdown field strength. However, excessive leads an increase MOS, resulting premature breakdown. Using optimized conditions, we LDMOSFETs obtained threshold (Vth), field-effect mobility (μFE) specific on-resistance (Ron-sp) from transfer curve (Id-Vg) output (Id-Vd) measurements. research findings provide valuable insights for process SiC.