The Effect of Diluted N2O Annealing Time on Gate Dielectric Reliability of SiC Metal-Oxide Semiconductor Capacitors and Characterization of Performance on SiC Metal-Oxide Semiconductor Field Effect Transistor

• DOI: 10.3390/electronics13030596
• Publication Date: 2024-01-31T15:44:24Z
• Authors: Zhihua Dong; Leifeng Jiang; Manqi Su; Chunhong Zeng; Hui Liu; Botong Li; Yuhua Sun; Qi Cui; Zhongming Zeng; Baoshun Zhang

We performed dry oxidation on n-type silicon carbide (SiC), followed by annealing in diluted N2O, and subsequently fabricated n-type MOS structures. The study aimed to investigate the impact of different annealing times on the trap charges near the SiC/SiO2 interface and the reliability of the gate dielectric. Capacitance-voltage (C-V) and current-voltage (I-V) measurements of the n-type MOS revealed that increasing the annealing time with N2O effectively reduces the density of electron traps near the SiC/SiO2 interface, mitigates the drift in flat-band voltage and enhances the oxide breakdown field strength. However, excessive annealing time leads to an increase in the flat-band voltage drift of the MOS, resulting in premature oxide breakdown. Using the optimized annealing conditions, we fabricated n-type LDMOSFETs and obtained the threshold voltage (Vth), field-effect mobility (μFE) and specific on-resistance (Ron-sp) from the transfer curve (Id-Vg) and output curve (Id-Vd) measurements. The research findings provide valuable insights for the gate oxidation process of SiC.