Hardware Optimized Modular Reduction

• DOI: 10.3390/electronics14030550
• Publication Date: 2025-01-29T16:10:39Z
• Authors: Alexander Magyari; Yuhua Chen

We introduce a modular reduction method that is optimized for hardware and outperforms conventional approaches. By leveraging calculated cycles combinatorial logic, we achieve remarkable 30% in power usage, 27% Configurable Logic Blocks (CLBs), 42% fewer look-up tables (LUTs) than the implementation. Our Hardware-Optimized Modular Reduction (HOM-R) system can condense 256-bit input to four-bit base within single 250 MHz clock cycle. Further, our stands out from prevalent techniques, such as Barrett Montgomery reduction, by eliminating need multipliers or dividers, relying solely on addition customizable LUTs. This innovative frees up FPGA resources typically consumed power-intensive DSPs, offering compelling low-power, low-latency alternative diverse design needs.