Achieving Low-Latency, High-Throughput Online Partial Particle Identification for the NA62 Experiment Using FPGAs and Machine Learning

• DOI: 10.3390/electronics14091892
• Publication Date: 2025-05-07T09:18:20Z
• Authors: Pierpaolo Pertica...; Roberto Ammendola; Andrea Biagioni; Carlotta Chiarini; Andrea Ciardiello; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Michele Martinelli; Roberto Piandani; Luca Pontisso; Mauro Raggi; Cristian Rossi; Francesco Simula; Matteo Turisini; Piero Vicini; Alessandro Lonardo
• Keywords: Identification

FPGA-RICH is an FPGA-based online partial particle identification system for the NA62 experiment employing AI techniques. Integrated between readout of Ring Imaging Cherenkov detector (RICH) and low-level trigger processor (L0TP+), implements a fast pipeline to process in real-time RICH raw hit data stream, producing primitives containing elaborate physics information—e.g., number charged particles event—that L0TP+ can use improve decision efficiency. Deployed on single FPGA, combines classical processing with compact Neural Network algorithm achieve efficient event classification while managing challenging ∼10 MHz throughput requirement NA62. The streaming ensures ∼1 μs latency, comparable that detectors, allowing its seamless integration existing TDAQ setup as additional detector. Development leverages High-Level Synthesis (HLS) open-source hls4ml package software–hardware codesign workflow, enabling flexible reprogramming, debugging, performance optimization. We describe implementation full pipeline, classifier, their functional validation, metrics system’s current status outlook.