A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

• DOI: 10.3390/electronics8101116
• Publication Date: 2019-10-04T08:12:52Z
• Authors: Marina Yushkova; Alberto Sanchez; Angel de Castro; M. Sofía Martínez...
• Keywords: Implementation

The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because its advantages compared to traditional simulation techniques. This increase usage has caused new challenges related the improvement their performance and features like number output channels, while price HIL diminishing. At present, low-speed Digital-to-Analog Converters (DACs) starting be a commercial possibility two reasons. One lower other pin count, which determines FPGAs that are necessary handle those DACs. paper compares four filtering approaches for providing suitable data DACs, help filter high-speed input signals, discarding need using expensive DACS, therefore decreasing total cost implementations. Results show selection appropriate should based on type waveform relative importance dynamics versus area.