Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

• DOI: 10.3390/s24061891
• Publication Date: 2024-03-15T13:32:30Z
• Authors: Soongyu Kang; Seongjoo Lee; Yunho Jung
• Keywords: Edge device

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part modern life. For low-latency AI computation IoT there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) machine learning algorithm well-suited implementation on edge devices due to its simple and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it easy adjust structure learn additional data. Therefore, can provide real-time processing various sensor applications. However, previous accelerators have limited scalability when number increases. this paper, we propose network-on-chip (NoC)-based accelerator present results field-programmable gate array (FPGA). NoC effective solution managing massive interconnections. proposed utilizes hierarchical-star (H-star) topology, which efficiently handles large neurons, along routers specifically designed RCE-NN. These approaches result only slight decrease maximum operating frequency Consequently, 512 increased by 126.1% compared accelerator. This enhancement was verified two datasets gas sign language recognition, achieving accelerations up 54.8% time 45.7% time. scheme appropriate ensure while providing high-performance on-chip recognition.