The Design and Implementation of a High-Speed Parallel AES Crypto-Chip

• DOI: 10.4028/www.scientific.net/amr.468-471.1721
• Publication Date: 2012-02-27T13:56:20Z
• Authors: Jun Yang; Wei Ping Zhang; Ping Ping Shu; Xiao Jun Wang; Ga Zhao; Heng Fen Yang
• Keywords: Nios II

This paper direct to security and real-time requirements in high-speed network transmission processing, based on SOPC technology, design a High throughput AES encryption/ decryption processing unit with pipelining. The goal is optimize the hardware structure improve throughput, S-box parallel structure. Compared traditional crypto-chip has faster rate encryption less consumption of resources advantages. adopts VHDL description language, use Quartus II 8.0 for synthesis routing, this packaged an independent IP core, attached Altera provided Nios system, finally download test validation DE2 development platform.