The Design of Serial ATA Bus Control Chip

• DOI: 10.4304/jcp.5.4.524-532
• Publication Date: 2010-04-01T07:19:33Z
• Authors: Wei Cheng; Zhenghua Tan; Zhiliang Zhu; Guiran Chang
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

In a PC system, External storage interface is still bottleneck in spite of its continuous improving performance, contrast to the fast development CPU, memory, graphic chips. The transfer rate ATA protocol has been improved drastically from beginning 3.3MB/s current 133MB/s, but plate electrode parallel inevitably puzzled by clock skew, which limit increasing frequency and can not be improved. Serial compatible with Parallel software layer. Its greatly due serial embedded clock. This paper will discuss differences between protocol, describe hierarchical classification model. Last design for HPT183, parallel/serial bridge connection chip put forward. high speed integrated circuit design, data recovery troublesome task. this an all-digital module 1.5bps SATA implement introduced. contract other made analog circuit, easily it lower power consumption smaller area. being implemented HPT183 designed manufactured using 0.18um CMOS process. At end test performance index also provided.