QADAM: Quantization-Aware DNN Accelerator Modeling for Pareto-Optimality

• DOI: 10.48550/arxiv.2205.13045
• Publication Date: 2022-01-01
• Authors: Inci, Ahmet; Virupaksha, Siri ...; Jain, Aman; Thallam, Venkata ...; Ding, Ruizhou; Marculescu, Diana
• Keywords: FOS: Computer and information sciences; Computer Science - Machine Learning; Hardware Architecture (cs.AR); 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; Computer Science - Hardware Architecture; 7. Clean energy; Machine Learning (cs.LG)

As the machine learning and systems communities strive to achieve higher energy-efficiency through custom deep neural network (DNN) accelerators, varied bit precision or quantization levels, there is a need for design space exploration frameworks that incorporate quantization-aware processing elements (PE) into the accelerator design space while having accurate and fast power, performance, and area models. In this work, we present QADAM, a highly parameterized quantization-aware power, performance, and area modeling framework for DNN accelerators. Our framework can facilitate future research on design space exploration and Pareto-efficiency of DNN accelerators for various design choices such as bit precision, PE type, scratchpad sizes of PEs, global buffer size, number of total PEs, and DNN configurations. Our results show that different bit precisions and PE types lead to significant differences in terms of performance per area and energy. Specifically, our framework identifies a wide range of design points where performance per area and energy varies more than 5x and 35x, respectively. We also show that the proposed lightweight processing elements (LightPEs) consistently achieve Pareto-optimal results in terms of accuracy and hardware-efficiency. With the proposed framework, we show that LightPEs achieve on par accuracy results and up to 5.7x more performance per area and energy improvement when compared to the best INT16 based design.<br/>Accepted paper at the Machine Learning for Computer Architecture and Systems (MLArchSys) Workshop in conjunction with ISCA 2021. This is an extended version of arXiv:2205.08648<br/>