Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

• DOI: 10.5369/jsst.2020.29.2.82
• Publication Date: 2020-04-28T08:48:36Z
• Authors: Hyeunwoo Kwen; Sang-Hwan Kim; Jimin Lee; Pyung Choi; Jang-Kyoo Shin
• Keywords: Flash ADC

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using double-tail comparator for highspeed and low-power operations. The GBT is based on PMOSFET tied floating gate (n+ polysilicon) body that amplifies the photocurrent generated by incident light. A compares an input signal reference voltage returns output as either 0 or 1. processing speed power consumption of are superior over those conventional comparator. Further, use double-sampling circuit reduces standard deviation voltages. Therefore, proposed CMOS might have advantages, such low high speed. designed simulated 0.18 μm process.