Understanding voltage variations in chip multiprocessors using a distributed power-delivery network

• DOI: 10.5555/1266366.1266498
• Publication Date: 2007-04-16
• Authors: Meeta S. Gupta; Jarod L. Oatley; Russ Joseph; Gu-Yeon Wei; David Brooks
• Keywords: Power gating; Microprocessor; Power domains; Low-power electronics

Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and management require that designers be increasingly cognizant of variations. These variations, primarily due fast changes in current, can attributed architectural gating events reduce dissipation. In order study this problem, the authors propose a fine-grain, parameterizable model for power-delivery networks allows system localized, on-chip fluctuations high-performance microprocessors. Using model, analyze variations context next-generation chip-multiprocessor (CMP) architectures using both real applications synthetic current traces. They find activity distinct cores CMPs present several new design challenges when considering noise, they describe potentially problematic sequences are unique CMP