Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs

• DOI: 10.5555/2616606.2616995
• Publication Date: 2014-03-24
• Authors: Kitae Park; Geunho Kim; Taewhan Kim
• Keywords: Timing failure; Buffer (optical fiber); Digital clock manager

Recently, many works have shown that adjustable delay buffer (ADB) whose is dynamically can effectively solve the clock skew variation problem in designs with multiple power modes. However, all previous of ADB allocation inherently entail two critical limitations, which are adjusted delays by always increments and low cost sizing has never been or not primarily taken into account. To demonstrate how much overcoming limitations effective resolving constraint, we characterize types ADBs called CADB (capacitor based ADB) IADB (inverter show be decremented, violation some trees modes resolved applying together using only a small number IADBs CADBs.